1. Field
The following description relates to a cache control device for cache prefetching and a prefetching method using the cache control device.
2. Description of Related Art
In general, in computer architecture, a memory fetch instruction is a major hindrance to high-speed processing of a processor because it takes several hundreds to thousands of cycles to process the memory fetch instruction.
To overcome such problems, a cache, which is a high-speed buffer memory, is provided between memory and a processor. By storing accessed data or instruction, and thereby reducing a number of accesses to memory, a cache provides support to a processor for high-speed processing. Even with a small memory capacity, a cache can provide a faster access mechanism, compared to a memory. However, the use of a large cache may be limited by a processor's size, power, and cost.
For efficient use of a cache with a small capacity, latency due to a cache miss is minimized by increasing a probability of finding data or instructions, which are needed by a processor to process a program, in the cache.
That is, a goal may be to maximize a hit ratio of a cache. To this end, prefetching is employed in a cache. A processor is enabled to process a program without latency by predicting data or instructions, and prefetching the data or instructions into the cache.
For prefetching, a memory address locality technique may be used. The locality technique may be classified into temporal locality and spatial locality. Temporal locality refers to consecutive use of the same data within a given period of time, and spatial locality refers to the use of a data address that is close to the currently used data address in memory. However, even if data has low spatial locality or temporal locality, a delay may still occur.